power_drv.h

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00016 
00017 /* Copyright (c) 2007, Atmel Corporation All rights reserved.
00018  *
00019  * Redistribution and use in source and binary forms, with or without
00020  * modification, are permitted provided that the following conditions are met:
00021  *
00022  * 1. Redistributions of source code must retain the above copyright notice,
00023  * this list of conditions and the following disclaimer.
00024  *
00025  * 2. Redistributions in binary form must reproduce the above copyright notice,
00026  * this list of conditions and the following disclaimer in the documentation
00027  * and/or other materials provided with the distribution.
00028  *
00029  * 3. The name of ATMEL may not be used to endorse or promote products derived
00030  * from this software without specific prior written permission.
00031  *
00032  * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
00033  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00034  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
00035  * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
00036  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
00039  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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00041  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042  */
00043 
00044 
00045 #ifndef _POWER_DRV_H_
00046 #define _POWER_DRV_H_
00047 
00048 #ifdef  __GNUC__
00049    #include <avr/power.h>
00050 #endif
00051 
00052 #ifdef __GNUC__
00053 #ifndef CLKSEL0 
00054    #define CLKSEL0  _SFR_MEM8(0XD0)
00055 #endif
00056 #ifndef CLKSEL1 
00057    #define CLKSEL1  _SFR_MEM8(0XD1)
00058 #endif
00059 #ifndef CLKSTA 
00060    #define CLKSTA   _SFR_MEM8(0XD2)
00061 #endif
00062 #endif
00063 
00067 
00068 //_____ M A C R O S ________________________________________________________
00069 
00070 #define Setup_idle_mode()                (SMCR=0,SMCR |= (1<<SE))
00071 #define Setup_power_down_mode()                   (SMCR=0,SMCR |= (1<<SE)+(1<<SM1))
00072 #define Setup_adc_noise_reduction_mode()          (SMCR=0,SMCR |= (1<<SE)+(1<<SM0))
00073 #define Setup_power_save_mode()                          (SMCR=0,SMCR |= (1<<SE)+(1<<SM1)+(1<<SM0))
00074 #define Setup_standby_mode()                     (SMCR=0,SMCR |= (1<<SE)+(1<<SM2)+(1<<SM1))
00075 #define Setup_ext_standby_mode()                  (SMCR=0,SMCR |= (1<<SE)+(1<<SM2)+(1<<SM1)+(1<<SM0))
00076 
00086 
00087 #ifdef  __GNUC__
00088    #define Clear_prescaler()                       (clock_prescale_set(0))
00089 #else
00090    #define Clear_prescaler()                       (Set_cpu_prescaler(0))
00091 #endif
00092 
00102 #ifdef  __GNUC__
00103    #define Set_cpu_prescaler(x)                        (clock_prescale_set(x))
00104 #else
00105    extern void Set_cpu_prescaler(U8 x);
00106 #endif
00107 
00108 
00109 #define Sleep_instruction()              {asm("SLEEP");}
00110 
00111 //Backward compatibility
00112 #define Set_power_down_mode()              set_power_down_mode()
00113 #define Set_idle_mode()            set_idle_mode()
00114 
00115 //_____ D E C L A R A T I O N ______________________________________________
00116 
00117 void set_idle_mode(void);
00118 void set_power_down_mode(void);
00119 void set_adc_noise_reduction_mode(void);
00120 void set_power_save_mode(void);
00121 void set_standby_mode(void);
00122 void set_ext_standby_mode(void);
00123 
00132 #define Enter_idle_mode()                 (set_idle_mode())
00133 
00142 #define Enter_power_down_mode()           (set_power_down_mode())
00143 
00152 #define Enter_adc_noise_reduction_mode()  (set_adc_noise_reduction_mode())
00153 
00162 #define Enter_power_save_mode()           (set_power_save_mode())
00163 
00172 #define Enter_standby_mode()              (set_standby_mode())
00173 
00182 #define Enter_ext_standby_mode()          (set_ext_standby_mode())
00183 
00184 
00186 
00187 
00188 
00189 
00193 
00194 //_____ M A C R O S ________________________________________________________
00195 
00196 // Clock control
00197 #define   Enable_external_clock()       (CLKSEL0 |= (1<<EXTE))
00198 #define   Disable_external_clock()      (CLKSEL0 &= ~(1<<EXTE))
00199 #define   Enable_RC_clock()             (CLKSEL0 |= (1<<RCE))
00200 #define   Disable_RC_clock()            (CLKSEL0 &= ~(1<<RCE))
00201 
00202 // Clock state
00203 #define   External_clock_ready()        (((CLKSTA&(1<<EXTON)) != 0) ? TRUE : FALSE)
00204 #define   RC_clock_ready()              (((CLKSTA&(1<<RCON)) != 0) ? TRUE : FALSE)
00205 
00206 // Clock selection
00207 #define   Select_external_clock()       (CLKSEL0 |= (1<<CLKS))
00208 #define   Select_RC_clock()             (CLKSEL0 &= ~(1<<CLKS))
00209 
00210 // Clock settings : when using a clock source, only the other clock source setting can be modified
00211 // Set the source setting of the next clock source to use before switching to it
00212 #define   Load_ext_clock_config(cfg)    (CLKSEL1 = (CLKSEL1&0xF0) | ((cfg&0x0F)<<EXCKSEL0), \
00213                                          CLKSEL0 = (CLKSEL0&0xCF) | (((cfg&0x30)>>4)<<EXSUT0))
00214 
00215 #define   Load_RC_clock_config(cfg)     (CLKSEL1 = (CLKSEL1&0x0F) | ((cfg&0x0F)<<RCCKSEL0), \
00216                                          CLKSEL0 = (CLKSEL0&0x3F) | (((cfg&0x30)>>4)<<RCSUT0))
00217 
00218 //_____ C L O C K   D E F I N I T I O N S ______________________________________
00219 // Configuration byte defined as SUT<1:0> & CKSEL<3:0> (CKSEL0 is the LSb)
00220 
00221 // Interal RC oscillator (frequency between 7.3 and 8.1 MHz)
00222 #define   OSC_INTRC_0MS                  0x02
00223 #define   OSC_INTRC_4MS                  0x12
00224 #define   OSC_INTRC_65MS                 0x22
00225 
00226 // External crystal, frequency between 0.3 and 0.9 MHz
00227 #define   OSC_XTAL_RANGE1_258CK_4MS      0x08
00228 #define   OSC_XTAL_RANGE1_258CK_65MS     0x18
00229 #define   OSC_XTAL_RANGE1_1KCK_0MS       0x28
00230 #define   OSC_XTAL_RANGE1_1KCK_4MS       0x38
00231 #define   OSC_XTAL_RANGE1_1KCK_65MS      0x09
00232 #define   OSC_XTAL_RANGE1_16KCK_0MS      0x19
00233 #define   OSC_XTAL_RANGE1_16KCK_4MS      0x29
00234 #define   OSC_XTAL_RANGE1_16KCK_65MS     0x39
00235 
00236 // External crystal, frequency between 0.9 and 3 MHz
00237 #define   OSC_XTAL_RANGE2_258CK_4MS      0x0A
00238 #define   OSC_XTAL_RANGE2_258CK_65MS     0x1A
00239 #define   OSC_XTAL_RANGE2_1KCK_0MS       0x2A
00240 #define   OSC_XTAL_RANGE2_1KCK_4MS       0x3A
00241 #define   OSC_XTAL_RANGE2_1KCK_65MS      0x0B
00242 #define   OSC_XTAL_RANGE2_16KCK_0MS      0x1B
00243 #define   OSC_XTAL_RANGE2_16KCK_4MS      0x2B
00244 #define   OSC_XTAL_RANGE2_16KCK_65MS     0x3B
00245 
00246 // External crystal, frequency between 3 and 8 MHz
00247 #define   OSC_XTAL_RANGE3_258CK_4MS      0x0C
00248 #define   OSC_XTAL_RANGE3_258CK_65MS     0x1C
00249 #define   OSC_XTAL_RANGE3_1KCK_0MS       0x2C
00250 #define   OSC_XTAL_RANGE3_1KCK_4MS       0x3C
00251 #define   OSC_XTAL_RANGE3_1KCK_65MS      0x0D
00252 #define   OSC_XTAL_RANGE3_16KCK_0MS      0x1D
00253 #define   OSC_XTAL_RANGE3_16KCK_4MS      0x2D
00254 #define   OSC_XTAL_RANGE3_16KCK_65MS     0x3D
00255 
00256 // External crystal, frequency between 8 and 16 MHz
00257 #define   OSC_XTAL_RANGE4_258CK_4MS      0x0E
00258 #define   OSC_XTAL_RANGE4_258CK_65MS     0x1E
00259 #define   OSC_XTAL_RANGE4_1KCK_0MS       0x2E
00260 #define   OSC_XTAL_RANGE4_1KCK_4MS       0x3E
00261 #define   OSC_XTAL_RANGE4_1KCK_65MS      0x0F
00262 #define   OSC_XTAL_RANGE4_16KCK_0MS      0x1F
00263 #define   OSC_XTAL_RANGE4_16KCK_4MS      0x2F
00264 #define   OSC_XTAL_RANGE4_16KCK_65MS     0x3F
00265 
00266 // External clock
00267 #define   OSC_EXTCLK_0MS                 0x00
00268 #define   OSC_EXTCLK_4MS                 0x10
00269 #define   OSC_EXTCLK_65MS                0x20
00270 
00271 
00272 //_____ D E C L A R A T I O N ______________________________________________
00273 
00274 void Clock_switch_external(void);
00275 void Clock_switch_internal(void);
00276 
00278 
00279 
00280 #endif  // _POWER_DRV_H_
00281 

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